Embodiments relate to a semiconductor device, and more particularly to a technology for detecting a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of device characteristics and reliability.
Among packaging technologies of semiconductor integrated circuits (ICs), a three-dimensional (3D) stack technology has been rapidly developed to increase packaging density and reduce the size of electronic components, resulting in production of high-performance semiconductor devices. A 3D stacked package is formed by stacking a plurality of chips that have the same or different memory capacity, and is generally called a chip stack package.
A chip stack package can be mass produced at a relatively reduced cost compared to a single-layered chip package. However, in a stack chip package, as the number and size of stacked chips increase, a line space for electrical connection of the stacked chips may be reduced to an insufficient size.
In order to address the above-mentioned issues, a Through Silicon Via (TSV) structure has been proposed to implement a stack chip package. In more detail, after forming a TSV in each chip in a wafer, physical and electrical connection between chips is vertically achieved by the TSV.
However, if the TSV is repetitively exposed to heat treatment during a fabrication process, then a metallic material (e.g., Cu ion) contained in the TSV may by diffusing or permeating into an active region of the semiconductor device. As a result, electrical characteristics of a package of semiconductor devices may be deteriorated.